HIL techniques are increasingly used for test purposes because of their advantages over classical simulations. FPGAs are becoming popular in HIL systems because of their parallel computing capabilities. In most cases, FPGAs are mainly used for signal processing like input PWM sampling and conditioning while there are also processors to model the system. However, there are other HIL systems that implement the model in the FPGA. For FPGA implementation and regarding the arithmetics, there are two main possibilities: fixed-point and floating-point. Fixed-point is the best choice only when real-time simulations with small simulation steps are needed, while floatingpoint is the common choice because of its flexibility and ease of use. This paper presents a novel hybrid arithmetic for FPGAs called parametrizable fixed-point which takes advantage of both arithmetics as the internal operations are accomplished using simple signed integers while the point location of the variables can be adjusted as necessary without redesigning the model of the plant. Experimental results show that a buck converter can be modeled using this novel arithmetic with a simulation step below 20 ns. Besides, the experiments prove that the proposed model can be adjusted to any set of values (voltages, currents, capacitances, etc.) keeping its accuracy without resynthesizing, showing the big advantage over fixed-point arithmetic.

HIL techniques are increasingly used for test purposes because of their advantages over classical simulations. FPGAs are becoming popular in HIL systems because of their parallel computing capabilities. In most cases, FPGAs are mainly used for signal processing like input PWM sampling and conditioning while there are also processors to model the system. However, there are other HIL systems that implement the model in the FPGA. For FPGA implementation and regarding the arithmetics, there are two main possibilities: fixed-point and floating-point. Fixed-point is the best choice only when real-time simulations with small simulation steps are needed, while floatingpoint is the common choice because of its flexibility and ease of use. This paper presents a novel hybrid arithmetic for FPGAs called parametrizable fixed-point which takes advantage of both arithmetics as the internal operations are accomplished using simple signed integers while the point location of the variables can be adjusted as necessary without redesigning the model of the plant. Experimental results show that a buck converter can be modeled using this novel arithmetic with a simulation step below 20 ns. Besides, the experiments prove that the proposed model can be adjusted to any set of values (voltages, currents, capacitances, etc.) keeping its accuracy without resynthesizing, showing the big advantage over fixed-point arithmetic.